Conventionally, a vertical CJFET made of SIC substrate includes a N channel JFET and a P channel JFET. The SiC material has semi-insulating (i.e., SI) property. The CJFET is disclosed in, for example, U.S. Pat. No. 6,503,782 and US 2007/0012946. In the CJFET, an impurity layer formed on the SiC substrate is divided by a trench etching method so that the N channel JFET region and the P channel JFET region are separated from each other. Thus, the N channel JFET region is isolated from the P channel JFET region.
Further, a vertical type CMOS transistor made of a SiC substrate is disclosed in, for example, U.S. Pat. No. 6,344,663. In the CMOS transistor, a PN separation technique is used, so that the N channel MOS transistor and the P channel MOS transistor are isolated from each other.
However, in the above cases, when the N channel JFET and the P channel JFET are isolated from each other by a trench etching method, an etched region provides a trench, which remains on the surface of the substrate. Thus, manufacturing steps are complicated since the surface of the substrate includes a step. For example, when an impurity layer is formed by an ion implantation method, it is difficult to form a mask because of the step on the surface of the substrate. Further, when a wiring layer is formed, the wiring layer is patterned under a condition that the wiring layer is disposed on the step. Thus, comparing with a case where the wiring layer is formed on a flat surface of the substrate, a manufacturing process is made difficult. Accordingly, it is required to provide a device having a flat surface without any step.
Since a structure shown in U.S. Pat. No. 6,344,663 provides isolation between the N channel MOS transistor and the P channel MOS transistor, an electric element can be formed on a flat surface of the substrate. However, when the device is used with high frequency, a noise may be transmitted. Further, when the device is used at high temperature, a current may be leaked.
Regarding a silicon based device, a trench separation structure is formed with using a SOI substrate. Thus, a trench is formed on a silicon layer to reach the embedded insulation film. When an insulation film is embedded in the trench, an element separation structure is formed by the insulation film in the trench. However, regarding a SiC based device, it is necessary to perform a high temperature step such as an activation step for an impurity. Thus, an insulation film such as an oxide film may be deformed in the high temperature step. Thus, it is difficult to apply the above technique in the silicon based device.